Firmware ======== This repository stores a collection of VHDL modules developed as part of the HotRIO project. The primary objective of this repository is to provide a centralized resource for reusable VHDL modules. Repository Structure -------------------- This repository follows a similar structure to a vertical project, defined in the Quality Assurance documentation `Here `_. Each module is stored in a directory inside 'Source/modules/' with the following subdirectory structure: :: . ├── ip_cores ├── globals └── modules/ └── module_name/ ├── hdl/ │ ├── module_name.vhd │ ├── supporting_ip1.vhd │ ├── supporting_ip2.vhd │ └── ... ├── sim/ │ ├── module_name_tb.vhd │ └── module_name_vunit.py └── test/ ├── module_name_test.vhd ├── module_name_test.lpf └── module_name_test.ldc To facilitate the use of automatic tools for testing a building the projects, the following files should be present in the module directory: - .vhd file with the module name inside of the hdl folder. This module should be the top-level entity of the module. - Testbench file with the module name, plus '_tb' inside of the sim folder. If Vunit is used, an associated python file must be present with the same name. - Test file with the module name, plus '_test' inside of the test folder. Moreover, a .lpf and a .ldc file must be present in the same folder. This test should target physical test on the FPGA development board (if applicable). .. https://tree.nathanfriend.io/?s=(%27options!(%27fancy6~fullPath!false~trailingSlash6~rootDot6)~9(%279%27ip_cores3globals3As30-8hdl*-41427...8sim*-_tb7-_vunit.py8B5vhd5lpf5ldc%27)~version!%271%27)*80-A_name0%20%203%5Cn47supporting_ip5*-_B.6!true7.vhd*83009source!AmoduleBtest%01BA98765430-* Ip cores ~~~~~~~~ The Ip cores are defined as the modules that are vendor-specific and fpga-specific. These modules are used to build the test projects for the modules. .. list-table:: :header-rows: 1 * - Module - Description * - :doc:`ecp5_dual_wrapper_8b ` - Custom wrapper for the ecp5 dual. Globals ~~~~~~~ The 'globals' package must be included in every HotRIO project as it contains important constants for HotRIO and for the PCS communication. :doc:`Globals package link ` Modules ~~~~~~~ .. list-table:: :header-rows: 1 * - Module - Description * - :doc:`adc_interface ` - Interface module for the ADCs. * - :doc:`cfg_regs ` - Registers modules and muxes. * - :doc:`cfg_spi ` - SPI configuration module. * - :doc:`clock_mux ` - Glitchless clock multiplexer with no hardware IP usage * - :doc:`crio_interface ` - Interface module for the communication with a compact-RIO * - :doc:`delay_counter ` - Counts the clock cycles between two signals. * - :doc:`ethernet_ipv4_udp_formatter ` - Packages data from a fifo into a ethernet frame (using udp). * - :doc:`hotrio_master_rx ` - Hotrio Master RX module. * - :doc:`hotrio_master_tx ` - Hotrio Master TX module. * - :doc:`hotrio_slave ` - Hotrio Slave module. * - :doc:`pulse_stretcher ` - Pulse stretcher module. * - :doc:`signal_cdc ` - Clock Domain Crossing (CDC) module. * - :doc:`vspi ` - Virtual SPI module. * - :doc:`i2c_master ` - I2C Master module. .. toctree:: :maxdepth: 2 :caption: Contents: modules/index ip_cores/index globals xilinx_scripts_guide