HotRIO slave (with self-transmit)
=================================

This module implements the same functionality of the hotrio-slave with the added feature that it can be configured to self-transmit. If the `slave_enable_i` is connected to the `rx_ready_o` output of the pcs, it enables the module to start self-transmitting when the incoming signal is loss. Note that in this configuration, a clock selector must be used to change the tx PLL reference of the PCS from the clock recovered from the incoming data, to the local crystal. 

Generics
--------
.. list-table::
   :header-rows: 1

   * - Name
     - Description
     - Default value
   * - HOTRIO_PCS_FREQUENCY
     - The frequency (in MHz) at which the packets are sent to the PCS. Used to calculate the number of clock cycles for the markers. This is used for the HotRIO master module.
     - 125

Ports
-----

.. list-table::
   :header-rows: 1

   * - Name
     - Mode
     - Description
     - Type
   * - pcs_tx_clk125
     - IN
     - 125MHz TX clock
     - std_logic
   * - pcs_tx_rst125n
     - IN
     - 125MHz TX reset
     - std_logic
   * - pcs_rx_data_i
     - IN
     - Input PCS data, must be synchronized to the 125MHz TX clock
     - std_logic_vector(7 downto 0)
   * - pcs_rx_kchar_i
     - IN
     - Input PCS k-character flag, must be synchronized to the 125MHz TX clock
     - std_logic
   * - slave_en_i
     - IN
     - Slave module enable signal, active when '1'
     - std_logic
   * - rx_address_i
     - IN
     - RX address input
     - std_logic_vector(7 downto 0)
   * - tx_hotrio_packet_i
     - IN
     - Input hotrio packet
     - hotrio_packet_t
   * - rx_hotrio_packet_o
     - OUT
     - Output hotrio packet
     - hotrio_packet_t
   * - rx_packet_new_o
     - OUT
     - New RX packet flag
     - std_logic
   * - rx_packet_valid_o
     - OUT
     - Valid RX packet flag
     - std_logic
   * - pcs_tx_data_o
     - OUT
     - Output PCS data
     - std_logic_vector(7 downto 0)
   * - pcs_tx_kchar_o
     - OUT
     - Output PCS k-character flag
     - std_logic
   * - packet_sent_o
     - OUT
     - Packet sent flag
     - std_logic
   * - slave_cnt_err_kchar_o
     - OUT
     - Slave count of k-character errors
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_cnt_err_data_o
     - OUT
     - Slave count of data errors
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_cnt_err_hrio_pid_o
     - OUT
     - Slave count of HRIO PID errors
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_cnt_err_parity_o
     - OUT
     - Slave count of parity errors
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_cnt_packets_received_o
     - OUT
     - Slave count of received packets
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_cnt_valild_packets_received_o
     - OUT
     - Slave count of valid received packets
     - std_logic_vector(CONFIG_DATA_WIDTH - 1 downto 0)
   * - slave_sync_o
     - OUT
     - Slave synchronization flag
     - std_logic


\* Defined in the :doc:`Globals package </firmware/globals>`

Dependencies
------------

.. list-table::
   :header-rows: 1

   * - Name
     - Motivation
   * - :doc:`globals </firmware/globals>`
     - Types definition and HotRIO constants.
   * - :doc:`signal_cdc </firmware/modules/signal_cdc>`
     - Used to synchronize the input reset
   * - :doc:`hotrio_master_tx </firmware/modules/hotrio_master_tx>`
     - Used to self-transmit

Implementation details
----------------------

This core consists of three main components: a HotRIO slave, a HotRIO master transmitter (tx), and a switch. The incoming PCS data is processed by the HotRIO slave, which decodes the data, synchronizes with it, and forwards it to the output. Simultaneously, the HotRIO master tx module generates HotRIO frames, populated with the input packets received by this module (tx_hotrio_packet_i). These two data streams are fed into a multiplexer (mux) controlled by the `slave_en_i` signal. When this signal is high, the output from the slave module is selected, otherwise, the output from the master is directed to the module's output.