Octo-SPI interface
==================

The **octo_spi** module implements a half-duplex Octo-SPI interface for communication between a microcontroller and an ECP5U FPGA. This interface is meant to enable fast data transfer between the devices. The MCU acts as master, starting read and write transactions from software. The FPGA acts as slave, either receiving data from the MCU or queueing data for transmission to the MCU.

The MCU is made aware of the status of this interface through two interrupt lines. ``interrupt(0)`` notifies that the FPGA is ready to accept a read, while ``interrupt(1)`` notifies that it's ready to accept a write.

The FPGA logic can be connected to the module through a TX channel and an RX channel, each consisting of a FIFO interface. FIFO width is fixed to 8 bits, while depth can be configured separately for TX and RX.

The TX interface features two inputs (8-bit data and write enable) and one output (full flag). The write enable must be pulsed high for a number of cycles equal to the TX packet size configured via generic. This pulse must not start when the full flag is high, but it can and should finish after the right number of cycles even if full goes high during its assertion.

The RX interface features one input (read enable) and three outputs (8-bit data, valid flag, empty flag). The read enable must be pulsed high for a number of cycles equal to the RX packet size configured via generic. This pulse must not start when the empty flag is high, but it can and should finish after the right number of cycles even if the empty flag goes high during its assertion. After the assertion of read enable, the valid flag will notify the availability of the requested data byte.

Module interface description
----------------------------

.. vhdlentity::
   :file: ../Firmware/Source/modules/octo_spi/hdl/octo_spi.vhd
   :entity: octo_spi