Register tree components
========================

The following modules are the building blocks assembled by *Firmware/Scripts/register_tree_gen.py* into register tree structures.

reg_rw
------

Generic:

- ``default_g``: This value will be set after reset release. If unspecified, zero is assumed.

Ports:

- ``clk_fpga_i``: Input clock.
- ``rstn_i``: Synchronous active-low reset.
- ``command_i``: Specifies what operation shall be carried out. 0 = read, 1 = write.
- ``cmd_valid_i``: 1-cycle pulse to request a read or write of the register's contents.
- ``mosi_data_i``: Serial line where data to be written into the register is received.
- ``reply_valid_o``: 1-cycle pulse to notify the start of transmission of data to be read by "regtree_access".
- ``miso_data_o``: Serial line where data is serialized for transmission to "regtree_access".
- ``core_data_o``: 16-bit parallel bus for the FPGA to access this register's data.

This module is going to be used mainly to control other modules' behavior. A default state can be specified with the ``default_g`` generic.

reg_ro
------

Ports:

- ``clk_i``: Input clock.
- ``rstn_i``: Synchronous active-low reset.
- ``cmd_valid_i``: 1-cycle pulse to request a read of the register's contents.
- ``reply_valid_o``: 1-cycle pulse to notify the start of transmission of data to be read by "regtree_access".
- ``miso_data_o``: Serial line where data is serialized for transmission to "regtree_access".
- ``core_data_i``: 16-bit parallel bus for the FPGA to write data into this register.

This module is going to be used mainly to read status values generated from other modules. For example, error bits, status bits, or values.

reg_const
---------

Generic:

- ``default_g``: This value will be set after reset release. It must be specified for this register type.

Ports:

- ``clk_i``: Input clock.
- ``rstn_i``: Synchronous active-low reset.
- ``cmd_valid_i``: 1-cycle pulse to request a read of the register's contents.
- ``reply_valid_o``: 1-cycle pulse to notify the start of transmission of data to be read by "regtree_access".
- ``miso_data_o``: Serial line where data is serialized for transmission to "regtree_access".
- ``core_data_o``: 16-bit parallel bus for the FPGA to access this register's data.

This module is going to be used mainly to specify static information such as firmware versions, dates or fixed configurations.

reg_demux
---------

Generic:

- ``n_outputs_g``: Sets the number of outputs. The default value is 8.

Ports:

- ``clk_i``: Input clock.
- ``rstn_i``: Synchronous active-low reset.
- ``address_i``: Controls to which output the input signal is propagated in this demux and in the downstream demux modules.
- ``command_i``: Command received from the upstream demux to be sent to the downstream register selected by the address. 
- ``cmd_valid_i``: Valid pulse received from the upstream demux to be sent to the downstream register selected by the address.
- ``data_i``: Data bit received from the upstream demux to be sento to the downstream register selected by the address.
- ``command_o``: Output vector of length ``n_outputs_g``. The value of ``command_i`` is copied in all bits of this vector.
- ``cmd_valid_o``: Output vector of length ``n_outputs_g``. The value of ``cmd_valid_i`` is copied to the bit of this vector selected by the address, while the other bits are kept low.
- ``data_o``: Output vector of length ``n_outputs_g``. The value of ``data_i`` is copied in all bits of this vector.

This demultiplexer is a synchronous design; the outputs are registered, thus becoming available with one clock cycle of delay. This is done to accommodate deep registers trees where signal propagation times can be a problem. The reset only acts on ``cmd_valid_o``, as all other values are ignored when this signal is low.

reg_mux
-------

Ports:

- ``clk_i``: Input clock.
- ``rstn_i``: Synchronous active-low reset.
- ``valid_i``: Input vector of unconstrained length, where valid pulses from upstream registers/muxes are collected.
- ``data_i``: Input vector with the same length as ``valid_i``, collecting data bits produced by registers during read operations.
- ``valid_o``: Single-bit output set to 1 whenever at least 1 bit is high in ``valid_i``.
- ``data_o``: Single-bit output set to 1 whenever at least 1 bit is high in ``data_i``.

This modules behaves as a registered OR gate, reducing the input vectors after one clock cycle of latency.