Configuration Registers
=======================

This module contains the building blocks of the configuration registers tree. Six modules are defined:

- ``reg_ro.vhd``: Read-only register from the point of view of the MCU. The FPGA can write this register.
- ``reg_rw.vhd``: Read-write register from the point of view of the MCU. The FPGA can only read this register.
- ``reg_const.vhd``: Constant register. Both the MCU and the FPGA can only read this register.
- ``reg_demux.vhd``: Contains a component that can switch the control signals from ``regtree_access`` to a register chosen with an address.
- ``reg_mux.vhd``: Complementary to the demux, can route the output of the selected register to one common signal.
- ``regtree_access.vhd``: Implements the state machine that interprets commands from SPI, sends requests to the register tree and receives replies.

Register tree components are not meant to be used standalone. Instead, they should be combined in an autogenerated module produced by "register_tree_gen.py", found in *Firmware/Scripts*. A guide on the usage of the script is provided here:

.. toctree::

   registers_map_documentation

In the following pages, the portlists and behaviour of each component are explained.

.. toctree::

   regtree_access
   cfg_regs