HotRIO Sideband Master Sub-Block
The HotRIO Sideband Master Sub-Block is a sideband-interface sub-block that provides the microcontroller with access to the sideband communication channel of a HotRIO Master module. This module will stem from a HotRIO Master communication-interface, although not every HotRIO Master may be associated with a sideband interface
This interface is the way the microcontroller can interact with the sideband channel by writting and reading from/to the FIFOs of the sideband channel.
As described in the corresponding section, the position of this sub-block depends on the ordering of preceding blocks and on the size of the Hardware Interfaces block. Consequently, the base address of this sub-block is parameter-dependent. In this document, all register addresses are specified relative to an offset.
Sub-Block header
The sub-block starts with a constant (CONST) header containing:
an 8-bit identifier for this sub-block type; and
an 8-bit field indicating optional features available in this sub-block.
For this sub-block, no optional features are defined; therefore, the feature field is reserved. The sub-block ID is 1.
Status register
The HotRIO Master Sideband Sub-Block provides a status register with diagnostic indicators that describe the current state of the sideband channel.
This register contains flags that indicate whether the channel is available for communication, whether the RX FIFO is full (and therefore must be serviced by the microcontroller), and the current master address.
Any change in sideband status observed through this register shall be signaled by asserting the Sideband-interface status flag in the Interrupt register.
Interface
The HotRIO Master sideband channel interface to the microcontroller consists of four registers. Two FIFOs are managed through these registers: one FIFO for the RX direction and one FIFO for the TX direction. The microcontroller shall read from the RX FIFO and write to the TX FIFO.
To service the FIFOs, the microcontroller accesses each FIFO through a single register that acts as the FIFO access point. By issuing a “read/write with no increment” operation, the register tree performs multiple read or write operations on the same register address, thereby transferring multiple bytes to or from the selected FIFO.
To determine how much data can be read from or written to the FIFOs, the number of available bytes is provided in a dedicated register associated with each FIFO.
The sideband interface register map is as follows:
Diagnostics
[0x0000] - Master sideband status (RO)
Sideband ready
AutoAddressing ongoing
Maximum address auto-addressed
Register Master sideband status with access policy (RO)
Signals:
Maximum address auto-addressed [0,7]
AutoAddressing ongoing [8,8]
Sideband ready [9,9]
[0x0001] - Master sideband control (RW)
Start autoaddressing
Register Master sideband control with access policy (RW)
Signals:
Start autoaddressing [0,0]
[0x0002] - TX register (RW)
Address to send to
Data to send
Register TX register with access policy (RW)
Signals:
Data to send [0,7]
Address to send to [8,15]
[0x0003] - RX register (RO)
Address received
Data received
Register RX register with access policy (RO)
Signals:
Data received [0,7]
Address received [8,15]
[0x0004] - RX FIFO level (RO)
RX FIFO level
Register RX FIFO level with access policy (RO)
Signals:
RX FIFO level [0,15]
[0x0005] - TX FIFO level (RO)
TX FIFO level
Register TX FIFO level with access policy (RO)
Signals:
TX FIFO level [0,15]