Firmware

This repository stores a collection of VHDL modules developed as part of the HotRIO project. The primary objective of this repository is to provide a centralized resource for reusable VHDL modules.

Repository Structure

This repository follows a similar structure to a vertical project, defined in the Quality Assurance documentation Here. Each module is stored in a directory inside ‘Source/modules/’ with the following subdirectory structure:

.
├── ip_cores
├── globals
└── modules/
   └── module_name/
      ├── hdl/
      │   ├── module_name.vhd
      │   ├── supporting_ip1.vhd
      │   ├── supporting_ip2.vhd
      │   └── ...
      ├── sim/
      │   ├── module_name_tb.vhd
      │   └── module_name_vunit.py
      └── test/
            ├── module_name_test.vhd
            ├── module_name_test.lpf
            └── module_name_test.ldc

To facilitate the use of automatic tools for testing a building the projects, the following files should be present in the module directory:

.vhd file with the module name inside of the hdl folder. This module should be the top-level entity of the module.
Testbench file with the module name, plus ‘_tb’ inside of the sim folder. If Vunit is used, an associated python file must be present with the same name.
Test file with the module name, plus ‘_test’ inside of the test folder. Moreover, a .lpf and a .ldc file must be present in the same folder. This test should target physical test on the FPGA development board (if applicable).

Ip cores

The Ip cores are defined as the modules that are vendor-specific and fpga-specific. These modules are used to build the test projects for the modules.

Module	Description
ecp5_dual_wrapper_8b	Custom wrapper for the ecp5 dual.

Globals

The ‘globals’ package must be included in every HotRIO project as it contains important constants for HotRIO and for the PCS communication.

Globals package link

Modules

Module	Description
adc_interface	Interface module for the ADCs.
cfg_regs	Registers modules and muxes.
cfg_spi	SPI configuration module.
clock_mux	Glitchless clock multiplexer with no hardware IP usage
crio_interface	Interface module for the communication with a compact-RIO
delay_counter	Counts the clock cycles between two signals.
ethernet_ipv4_udp_formatter	Packages data from a fifo into a ethernet frame (using udp).
hotrio_master_rx	Hotrio Master RX module.
hotrio_master_tx	Hotrio Master TX module.
hotrio_slave	Hotrio Slave module.
pulse_stretcher	Pulse stretcher module.
signal_cdc	Clock Domain Crossing (CDC) module.
vspi	Virtual SPI module.
i2c_master	I2C Master module.