HotRIO Sideband Slave Sub-Block
The HotRIO Sideband Slave Sub-Block is a sideband-interface sub-block that provides the microcontroller with access to the sideband communication channel of a HotRIO Slave module. This module will stem from a HotRIO Slave communication-interface, although not every HotRIO Slave may be associated with a sideband interface
This interface is the way the microcontroller can interact with the sideband channel by writting and reading from/to the FIFOs of the sideband channel.
As described in the corresponding section, the position of this sub-block depends on the ordering of preceding blocks and on the size of the Hardware Interfaces block. Consequently, the base address of this sub-block is parameter-dependent. In this document, all register addresses are specified relative to an offset.
Sub-Block header
The sub-block starts with a constant (CONST) header containing:
an 8-bit identifier for this sub-block type; and
an 8-bit field indicating optional features available in this sub-block.
For this sub-block, no optional features are defined; therefore, the feature field is reserved. The sub-block ID is 1.
[Offset + 0x0000] - Sub-block header (CONST)
Communications interface sub-block optional features
Communications interface sub-block type
Register Sub-block header with access policy (CONST)
Signals:
- Communications interface sub-block type [0,7] ID of this sideband interface sub-block. In this case it does correspond to the HotRIO Slave sideband sub-block ID
Default value : 3
- Communications interface sub-block optional features [8,15] Optional features field for this sub-block. In this case it is 0 as no optional features are avaialble
Default value : 0
Status register
The HotRIO Slave Sideband Sub-Block provides a status register with diagnostic indicators that describe the current state of the sideband channel.
This register contains flags that indicate whether the channel is available for communication, whether the RX FIFO is full (and therefore must be serviced by the microcontroller), and the current slave address.
Any change in sideband status observed through this register shall be signaled by asserting the Sideband-interface status flag in the Interrupt register.
[Offset + 0x0001] - HotRIO Slave sideband status register (RO)
Sideband RX FIFO full flag
Sideband channel active
Sideband slave address
Register HotRIO Slave sideband status register with access policy (RO)
Signals:
Sideband slave address [0,6] Current sideband address, as assigned by the master, could be reassigned during the auto-addressing operation by the master
Sideband channel active [7,7] Flag indicating if the sideband channel is active, if it is up for communication.
Sideband RX FIFO full flag [8,8] Flag indicating id the RX fifo is full, meaning that no more data can be received and, therefore, servicing is needed from the microcontroller
Interface
The HotRIO Slave sideband channel interface to the microcontroller consists of four registers. Two FIFOs are managed through these registers: one FIFO for the RX direction and one FIFO for the TX direction. The microcontroller shall read from the RX FIFO and write to the TX FIFO.
To service the FIFOs, the microcontroller accesses each FIFO through a single register that acts as the FIFO access point. By issuing a “read/write with no increment” operation, the register tree performs multiple read or write operations on the same register address, thereby transferring multiple bytes to or from the selected FIFO.
To determine how much data can be read from or written to the FIFOs, the number of available bytes is provided in a dedicated register associated with each FIFO.
The sideband interface register map is as follows:
[Offset + 0x0002] - HotRIO Slave sideband RX FIFO level (RO)
Slave RX FIFO level
Register HotRIO Slave sideband RX FIFO level with access policy (RO)
Signals:
Slave RX FIFO level [0,15] uint16 counter of the number of bytes available to read from the RX FIFO
[Offset + 0x0003] - HotRIO Slave sideband RX FIFO (RO)
Slave RX FIFO
Register HotRIO Slave sideband RX FIFO with access policy (RO)
Signals:
Slave RX FIFO [0,7] RX Fifo access register, FIFOs operate on a byte-level, so each entry of the FIFO is interfaced with the first 8 bits of this register
[Offset + 0x0004] - HotRIO Slave sideband TX FIFO level (RO)
Slave TX FIFO level
Register HotRIO Slave sideband TX FIFO level with access policy (RO)
Signals:
Slave TX FIFO level [0,15] uint16 counter of the number of free bytes remaining to write into the TX FIFO
[Offset + 0x0005] - HotRIO Slave sideband TX FIFO (RW)
Slave TX FIFO
Register HotRIO Slave sideband TX FIFO with access policy (RW)
Signals:
Slave TX FIFO [0,7] TX Fifo access register, FIFOs operate on a byte-level, so each entry of the FIFO is interfaced with the first 8 bits of this register
Diagnostics
TBD