Register tree access protocol

This documentation provides an overview and description of the VHDL module that implements the HotRIO register tree access protocol. The module is meant to grant access to an internal register tree through a SPI interface with 8-bit transmission units, but if needed it can also be used in combination with any other interfaces that send and receive bytes.

Note

The module is configured to accept addresses and data in the “Little-Endian” format. They are however converted to Big-Endian internally.

The module

Generics

Name	Description	Type	Default
addr_cmd_g	"set_address" command	std_logic_vector(7 downto 0)	"00100000"
read_cmd_g	"read" command	std_logic_vector(7 downto 0)	"01000000"
write_cmd_g	"write" command	std_logic_vector(7 downto 0)	"10000000"
rni_cmd_g	"write_no_inc" command	std_logic_vector(7 downto 0)	"01010000"
wni_cmd_g	"read_no_inc" command	std_logic_vector(7 downto 0)	"10010000"

Input signals

IN ports

Name	Description	Type
clk_i	system clock of the fpga	std_logic
rstn_i	active-low synchronous reset	std_logic
csn_sync_i	spi chip select or analogous control, synchronized with `clk_i`	std_logic
rx_pulse_i	1-cycle pulse when a new byte is available on `mosi_byte_i`	std_logic
mosi_byte_i	byte stream where commands, addresses and rw register data are received	std_logic_vector(7 downto 0)
reply_valid_i	1-cycle pulse received when the first bit of register data is available on `reg_data_i`	std_logic
reg_data_i	register data is 16-bit, but it is communicated 1 bit at a time in a 16-cycle burst. this stream is retrieved from the register tree	std_logic

Output signals

OUT ports

Name	Description	Type
miso_sel_o	high if the module wants to write to miso. use to multiplex internal spi devices	std_logic
miso_byte_o	outgoing byte stream consisting of data retrieved from the register tree	std_logic_vector(7 downto 0)
command_o	instruction to execute on the register: 0-->read, 1-->write	std_logic
cmd_valid_o	1-cycle pulse when msb is sent on `reg_data_o`. lsb is sent in the next cycle	std_logic
address_o	address of the register that shall receive the command	std_logic_vector(15 downto 0)
reg_data_o	register data is 16-bit, but it is communicated 1 bit at a time in a 16-cycle burst. this stream goes towards the register tree	std_logic

The protocol

The communication protocol is straightforward and consists of three fundamental commands:

Command	Default value
Set address	“00100000”
Read	“01000000”
Write	“10000000”
Read without increment	“01010000”
Write without increment	“10010000”

The commands are defined by the generics addr_cmd_g, read_cmd_g, write_cmd_g, rni_cmd_g and wni_cmd_g and they can be changed if needed. This is especially useful is more than one register tree needs to be instantiated in the same firmware.

The process begins with the microcontroller sending a command, which is 8 bits long. This is followed by data transmitted in 16-bit packets, using little-endian format. Sequential reads and writes are also supported. After completing an operation, the internal address automatically increments, allowing subsequent registers to be read or written without restarting the communication process.

A register tree transaction consists of a ‘set address’ operation followed by a ‘read’ or ‘write’ operation which can be prolonged as needed to read or write several registers in a row, or to read/write the same register multiple times if the ‘rni’ and ‘wni’ commands are used instead of ‘read’ and ‘write’. The interface connected to “regtree_access” must assert rstn_i whenever a transaction is not ongoing, and at least for three cycles of the system clock between two transactions.

The following waveform diagrams illustrate the expected stimuli from the interface that drives the module and the corresponding expected responses. The examples show how to read or write two consecutive 16-bit registers. If the rni and wni commands had been used in place of the read and write commands, the two read/write operations would have been executed at the same address instead.

Set address operation waveform

Write operation waveform

Read operation waveform