Modules

• ADC36xx Interface
  • Additional support modules
    • ADC clock generation
    • ADC register map SPI configuration
  • Ports
    • Clock inputs
    • Data inputs
    • Data outputs
  • Implementation Details
    • Data Acquisition
    • Data Decoding
    • Wire mode timing diagrams
• HotRIO backplane interfaces
  • Description of the interfaces
    • ADC interfaces
    • BUS interfaces
  • Automatic generation of backplane interfaces
    • JSON syntax
      • Master Piranha configuration
      • Expansion board configuration
    • Generated files
      • Lattice Preference Files (LPF)
      • VHDL code: Device-specific IP cores
      • VHDL code: Backplane interface wrapper
  • Backplane interface timing constraints
    • Clock period
    • I/O constraints
      • Clock to out
      • Input setup
    • Timing constraints example
• Glitchless Soft Logic Clock Mux
  • Ports
  • Implementation Details
• cRIO Interface Module
  • Compact RIO Interface overview
    • Normal Operation
    • Configuration and EEPROM Operation mode
  • Module Description
    • Generics
    • Ports
    • Implementation Details
      • Signals and Modes
  • CRIO Normal Module
    • Clock and Frequency Division
    • Transmit Path
    • Receive Path and Synchronization
    • Data Reception
  • cRIO Configuration Module
    • Architecture
    • Configuration Flow
    • SPI Timing
  • EEPROM Emulation Submodule
    • Functionality Overview
    • Core Processes
  • Requirements for cRIO Register Tree Integration
• compactRIO HotLink Receiver
  • Generics
  • Ports
  • Implementation details
    • Constants
    • Signal Descriptions
• compactRIO HotLink Transmitter
  • Generics
  • Ports
  • Implementation details
    • Constants
    • Signal Descriptions
• Delay counter
  • Generics
  • Ports
  • Dependencies
  • Implementation details
    • Input conditioning
    • Counter state machine
• DMP Module
  • Overview
  • Functional Overview
  • Entity Declaration
  • Internal Constants
  • Delay Measurement Principle
  • Signed Delta Calculation
    • Example
  • Delay Calculation
  • Finite State Machine (FSM)
  • State Descriptions
  • Reset Behavior
  • Output Valid Timing
  • Outputs
  • Design Assumptions
  • Typical Use Case
• Ethernet IPV4 UDP formatter
  • Generics
  • Ports
  • Input Interface
  • PCS Interface
  • Implementation Details
    • Packet Description
    • MAC header
    • IPV4 header
    • UDP header
  • SDN Header
    • Main state machine
    • Ipv4 checksum
    • Ethernet CRC32
    • Internal FIFO buffer details
• Fast Logic Solver
  • Reference document
  • Differences between original design and HotRIO version
    • Configuration interface changes
    • Fast Logic Solver code generation
    • Clock frequency increase
    • Input stage changes
    • Data feeder module
  • Module instantiation
    • Generics
    • Ports
• G0 Interrupt Controller
  • VHDL interface description
• HotRIO master rx
  • Detailed portlist
  • Dependencies
  • Implementation details
• HotRIO master tx
  • Detailed portlist
  • Dependencies
  • Implementation details
    • State machine
    • Marker generation
    • Parity bits generation
• HotRIO slave
  • Generics and ports
  • Dependencies
  • Implementation details
    • State machines
• HotRIO slave selftransmit (removed)
• Min/Max downsampler module
  • VHDL interface description
• Octo-SPI interface
  • Module interface description
• pulse_stretcher
  • Generics
  • Ports
  • Dependencies
  • Implementation details
    • Input conditioning
    • Counter
• Configuration Registers
  • Generating a Register Tree
    • Input Format
    • Usage
    • Example
    • Notes
  • Register tree access protocol
    • The module
    • The protocol
  • Register tree components
    • reg_rw
    • reg_ro
    • reg_const
    • reg_demux
    • reg_mux
• Scheduler RX
  • Overview
  • Source Dependencies
  • Detailed portlist
  • Generics
    • Generic Use Cases
  • Internal Architecture
    • Reset Behavior
    • Enable Behavior
    • Address Table Generation
    • Payload History Model
    • Circular Write Pointer
  • Finite State Machine
    • IDLE State
    • LOAD_ADDR State
    • WAIT_PACKET State
    • DECODE_ADDR State
    • STORE_UNICAST State
    • STORE_BROADCAST State
    • ERROR_ADDR State
  • Output Behavior
    • Latest Payload Outputs
    • Payload Valid Pulses
    • Invalid Address Pulse
  • Address Reload Behavior
• Scheduler TX Module
  • Overview
  • Detailed portlist
  • Source Dependencies
  • Generics
    • Generic Use Cases
  • Internal Architecture
    • Reset Behavior
    • Enable Behavior
    • Address Table Generation
    • Payload Capture
  • Finite State Machine
    • IDLE State
    • LOAD_ADDR State
    • RUN State
      • Address Update Priority
      • Broadcast Scheduling
      • Single Shared Payload Scheduling
      • Per-Slave Payload Scheduling
    • Round-Robin Index Operation
• Signal CDC
  • Introduction
  • Ports
• Timestamp counter with PPS synchronization
  • VHDL interface description
• Configurable threshold comparator module
  • VHDL interface description
• VSPI
  • Ports
  • Implementation Details
    • Multiplexer and Demultiplexer Logic
    • Synchronous CS
• i2c_master VHDL Module
  • Overview
  • Key Features
  • Module Overview
  • Generics
  • Ports
  • Implementation Details
  • Limitations
  • Usage Example
  • References
  • Authors