Modules

• ADC36xx Interface
  • Additional support modules
    • ADC clock generation
    • ADC register map SPI configuration
  • Ports
    • Clock inputs
    • Data inputs
    • Data outputs
  • Implementation Details
    • Data Acquisition
    • Data Decoding
    • Wire mode timing diagrams
• Configuration Registers
  • reg_ro
  • reg_rw
  • reg_mux
  • reg_demux
  • Example
  • Additional Notes
• Configuration SPI slave interface
  • Ports
  • SPI protocol
  • Implementation details
    • Submodules
    • SPI interface
    • State machine
• Glitchless Soft Logic Clock Mux
  • Ports
  • Implementation Details
• cRIO Interface Module
  • Compact RIO Interface overview
    • Normal Operation
    • Configuration and EEPROM Operation mode
  • Module Description
    • Generics
    • Ports
    • Implementation Details
      • Signals and Modes
  • CRIO Normal Module
    • Clock and Frequency Division
    • Transmit Path
    • Receive Path and Synchronization
    • Data Reception
  • cRIO Configuration Module
    • Architecture
    • Configuration Flow
    • SPI Timing
  • EEPROM Emulation Submodule
    • Functionality Overview
    • Core Processes
  • Requirements for cRIO Register Tree Integration
• compactRIO HotLink Receiver
  • Generics
  • Ports
  • Implementation details
    • Constants
    • Signal Descriptions
• compactRIO HotLink Transmitter
  • Generics
  • Ports
  • Implementation details
    • Constants
    • Signal Descriptions
• Delay counter
  • Generics
  • Ports
  • Dependencies
  • Implementation details
    • Input conditioning
    • Counter state machine
• Ethernet IPV4 UDP formatter
  • Generics
  • Ports
  • Input Interface
  • PCS Interface
  • Implementation Details
    • Packet Description
    • MAC header
    • IPV4 header
    • UDP header
  • SDN Header
    • Main state machine
    • Ipv4 checksum
    • Ethernet CRC32
    • Internal FIFO buffer details
• HotRIO master rx
  • Ports
  • Dependencies
  • Implementation details
• HotRIO master tx
  • Generics
  • Ports
  • Dependencies
  • Implementation details
    • State machine
    • Marker generation
    • Parity bits generation
• HotRIO slave
  • Ports
  • Dependencies
  • Implementation details
    • State machine
• HotRIO slave (with self-transmit)
  • Generics
  • Ports
  • Dependencies
  • Implementation details
• pulse_stretcher
  • Generics
  • Ports
  • Dependencies
  • Implementation details
    • Input conditioning
    • Counter
• Signal CDC
  • Introduction
  • Ports
• VSPI
  • Ports
  • Implementation Details
    • Multiplexer and Demultiplexer Logic
    • Synchronous CS
• i2c_master VHDL Module
  • Overview
  • Key Features
  • Module Overview
  • Generics
  • Ports
  • Implementation Details
  • Limitations
  • Usage Example
  • References
  • Authors