G0 Interrupt Controller

This module mediates the transfer of interrupt information from the FPGA to the STM32-G0 MCU in HotRIO boards.

Interrupts are generated by several interfaces in the HotRIO environment, and they should be transferred to the MCU via SPI register tree. There are constraints on how the FPGA should control the interrupt register for the MCU to be able to service the interrupts correctly:

• The hardware interrupt line to the MCU must be the logical OR of the interrupt vector stored in the register read by the MCU.

• The interrupt vector shall be cleared when the MCU reads it via register tree.

• After the interrupt vector has been cleared, no new interrupts must be added to it for the following 30 us.

• During this period, interrupt requests must be saved in an internal register to be added to the interrupt vector when it is ready to accept them.

These constraints are implemented into this module, allowing other firmware components to communicate their interrupt request to the MCU with a one-cycle pulse.

VHDL interface description

Generics

Name	Description	Type	Default
latch_timeout_g	time to wait after a read before new interrupts can be appended again to `irq_vector_o`	time	30 us
clk_period_g	period of `clk_i`	time	8 ns
n_interrupts_g	number of interrupt bits in `irq_vector_o`	positive	16

Input signals

IN ports

Name	Description	Type
clk_i	system clock of the fpga	std_logic
rstn_i	active-low synchronous reset	std_logic
irq_pulse_vector_i	vector of interrupt requests, each communicated as a one-cycle pulse	std_logic_vector(n_interrupts_g - 1 downto 0)
read_pulse_i	one-cycle pulse received when the mcu reads `irq_vector_o`	std_logic

Output signals

OUT ports

Name	Description	Type
irq_vector_o	vector of interrupts to be transferred to the mcu	std_logic_vector(n_interrupts_g - 1 downto 0)
hw_interrupt_o	hardware interrupt line to be connected to a dedicated pin of the mcu. high when there are unread interrupts in `irq_vector_o`	std_logic