Min/Max downsampler module

This module downsamples a data stream by selecting minimum and/or maximum values in each window. The window size can be configured as a generic, allowing any fixed downsampling factor. The module has two operation modes that determine which samples will be preserved from each window and which will be dropped:

• In mode 0, both the minimum and the maximum value of the window are provided to the user after enough input samples are received.

• In mode 1, only either the minimum or the maximum value of the window is provided to the user after enough input samples are received.

Downsampling is performed by asserting valid_o once every N valid_i pulses, where N = 2 * downsampling_factor_g in mode 0 and N = downsampling_factor_g in mode 1. This difference guarantees that the downsampling factor is respected even though every valid_o cycle corresponds to two valid values in mode 0 and only one in mode 1.

• In mode 0, when valid_o goes high two values are available to the user: data_o and data_min_o.

• In mode 1, when valid_o goes high, only data_o should be considered.

Input data is processed during each valid_i pulse. It is compared with the largest and smallest values previously found in the same window, updating one of these two variables if required. Comparisons can be set to signed or unsigned at runtime.

Note that in mode 1 the average value of the downsampled stream will be different from the average of the input stream.

Also note that changing signed_i or keep_min_i during operation of the module should be avoided, as it may cause the selection of an unexpected value in the current downsampling window.

VHDL interface description

Generics

Name	Description	Type	Default
mode_g	0 = output min and max value from each window. 1 = only output either min or max from each window	bit	Unspecified
data_width_g	width of input and output data in bits	positive	Unspecified
downsampling_factor_g	number of valid inputs that shall be acquired to generate a valid output	positive	Unspecified

Input signals

IN ports

Name	Description	Type
clk_i	system clock of the fpga	std_logic
rstn_i	active-low synchronous reset	std_logic
keep_min_i	0 = in mode 1, output the largest value in the window. 1 = in mode 1, output the smallest value in the window. only change while `rstn_i` is low	std_logic
signed_i	0 = unsigned comparison. 1 = signed comparison. only change while `rstn_i` is low	std_logic
data_i	input data to be downsampled	std_logic_vector(data_width_g - 1 downto 0)
valid_i	when high, the current value of `data_i` is processed by the module	std_logic

Output signals

OUT ports

Name	Description	Type
data_o	output data. in mode 0 it is the maximum value in the downsampling window; in mode 1 it depends on `keep_min_i`. should only be used when `valid_o` is high	std_logic_vector(data_width_g - 1 downto 0)
data_min_o	minimum value in the downsampling window. should only be used in mode 0 when `valid_o` is high	std_logic_vector(data_width_g - 1 downto 0)
valid_o	when high, an output value is ready on `data_o`	std_logic