Octo-SPI interface

The octo_spi module implements a half-duplex Octo-SPI interface for communication between a microcontroller and an ECP5U FPGA. This interface is meant to enable fast data transfer between the devices. The MCU acts as master, starting read and write transactions from software. The FPGA acts as slave, either receiving data from the MCU or queueing data for transmission to the MCU.

The MCU is made aware of the status of this interface through two interrupt lines. interrupt(0) notifies that the FPGA is ready to accept a read, while interrupt(1) notifies that it’s ready to accept a write.

The FPGA logic can be connected to the module through a TX channel and an RX channel, each consisting of a FIFO interface. FIFO width is fixed to 8 bits, while depth can be configured separately for TX and RX.

The TX interface features two inputs (8-bit data and write enable) and one output (full flag). The write enable must be pulsed high for a number of cycles equal to the TX packet size configured via generic. This pulse must not start when the full flag is high, but it can and should finish after the right number of cycles even if full goes high during its assertion.

The RX interface features one input (read enable) and three outputs (8-bit data, valid flag, empty flag). The read enable must be pulsed high for a number of cycles equal to the RX packet size configured via generic. This pulse must not start when the empty flag is high, but it can and should finish after the right number of cycles even if the empty flag goes high during its assertion. After the assertion of read enable, the valid flag will notify the availability of the requested data byte.

Module interface description

Generics

Name	Description	Type	Default
cmd_write_g	1-byte command to start a write transaction	std_logic_vector(7 downto 0)	x"AC"
cmd_read_g	1-byte command to start a read transaction	std_logic_vector(7 downto 0)	x"35"
rx_packet_size_g	number of bytes in each packet received from the mcu	integer range 4 to 32768	64
tx_packet_size_g	number of bytes in each packet transmitted to the mcu	integer range 4 to 32768	64
rx_fifo_depth_g	depth of the rx fifo in bytes. will be rounded to the next power of 2	integer range 64 to 32768	128
tx_fifo_depth_g	depth of the tx fifo in bytes. will be rounded to the next power of 2	integer range 64 to 32768	128

Input signals

IN ports

Name	Description	Type
clk_i	fpga system clock	std_logic
rstn_i	active-low synchronous reset	std_logic
wren_i	tx fifo write enable. causes `data_i` to be loaded into the tx fifo	std_logic
data_i	tx fifo data input. data provided here will be transmitted to the mcu in a future read transaction	std_logic_vector(7 downto 0)
rden_i	rx fifo read enable. moves one byte of received data from the rx fifo to `data_o`	std_logic
ospi_csn_i	octo-spi chip select	std_logic
ospi_clk_i	octo-spi clock (max 62.5 mhz)	std_logic

Output signals

OUT ports

Name	Description	Type
full_o	true if an additional packet would not fit in the tx fifo	std_logic
data_o	rx fifo data output. only read this when `valid_o` is high	std_logic_vector(7 downto 0)
valid_o	true if valid data is available in `data_o`	std_logic
empty_o	true if a full packet cannot be fetched from the rx fifo	std_logic
interrupt_o	2-bit interrupt bus to the mcu	std_logic_vector(1 downto 0)
cmd_err_cnt_o	number of wrong commands received	std_logic_vector(15 downto 0)
rx_err_cnt_o	number of packets lost to full rx fifo	std_logic_vector(15 downto 0)
tx_err_cnt_o	number of wrong packets sent due to empty tx fifo	std_logic_vector(15 downto 0)
last_cmd_o	last received command (independently of validity)	std_logic_vector(7 downto 0)
error_o	status flag, high when the interface is in the error state	std_logic

INOUT ports

Name	Description	Type
ospi_data_io	half-duplex octo-spi data bus	std_logic_vector(7 downto 0)