Configurable threshold comparator module

This comparator is designed to generate a digital interlock signal for fast protection systems based on the value of an analog protection variable. To provide the needed flexibility to adapt this function to most control applications, the module supports the following runtime configuration options:

• Signed or unsigned comparison.

• Choosing whether the allowed range for the control variable is above or below the assertion threshold.

• Two thresholds: one for the assertion of the alarm and a different one for its release.

• A time margin that must elapse before a value past the assertion threshold can raise the alarm.

• A time margin that must elapse before a value within the release threshold can release the alarm.

Time margins can be set to zero if the module should react immediately to a change in the input. The dual threshold feature is also optional and can be disabled by setting both thresholds to the same value.

Note

If dual threshold is used, the user is responsible to select the two values so that the assertion threshold is more permissive than the release threhsold, to obtain the desired hysteresis effect. If the two values are swapped, the module may become incapable of raising alarms.

The width of the input variable can be selected at compile-time with the width_g generic. The digital output of the module is active low, meaning that a low value represents the assertion of the interlock signal, while a high value represents normal operation of the system.

The module shall be kept in reset mode by maintaining rstn_i low while the configuration inputs are modified. The configuration inputs are unregistered, as they are meant to be stored in a register tree. False paths may be declared from the registers where the configuration inputs are stored to this module’s output if needed for timing closure. The meaning of each configuration input is listed in the section below.

VHDL interface description

Generics

Name	Description	Type	Default
width_g	width of the input and thresholds, expressed in bits	positive	Unspecified
time_width_g	width of the time limit values, expressed in bits	natural	Unspecified

Input signals

IN ports

Name	Description	Type
clk_i	system clock of the fpga	std_logic
rstn_i	active-low synchronous reset. when active, keeps `output_o` low regardless of `input_i`	std_logic
signed_i	0 = unsigned input and thresholds; 1 = signed input and thresholds	std_logic
th_direction_i	0 = alarm triggered by input at or above threshold; 1 = alarm triggered by input below threshold	std_logic
th_assert_i	threshold to trigger the alarm on `output_o`	std_logic_vector(width_g - 1 downto 0)
th_release_i	threshold to remove the alarm from `output_o`, returning to normal operation	std_logic_vector(width_g - 1 downto 0)
time_assert_i	time the input must stay continuously past `th_assert_i` before triggering the alarm, measured in cycles of `clk_i`	std_logic_vector(time_width_g - 1 downto 0)
time_release_i	time the input must stay continously within `th_release_i` before removing the alarm, measured in cycles of `clk_i`	std_logic_vector(time_width_g - 1 downto 0)
input_i	input to be compared against the thresholds to determine the value of the output	std_logic_vector(width_g - 1 downto 0)

Output signals

OUT ports

Name	Description	Type
output_o	0 = alarm active; 1 = normal operation	std_logic