Glitchless Soft Logic Clock Mux

This module takes as input a configurable number of clock signals and allows the user to dynamically select which of them should be propagated to the output. In doing so, it guarantees glitchless switching, meaning that no rapid clock transitions will be induced in the output when changing from one clock to another. Instead, the output will go low at a negative edge of the old clock and it will stay so for a variable time from 2 to 3 periods of the new clock, then the new clock will be visible at the output.

The module does not use any hardware IP clock multiplexers, instead relying on general FPGA fabric to perform the selection operation. This allows to save a scarce resource, as Lattice ECP5 devices only have few dedicated clock mux units; however, this entails some disadvantages as well:

• No meaningful output delay constraint can be applied to this module’s output, as its phase is unknown relative to the input clocks

• While the module guarantees the absence of glitches, timing violations can still be induced due to increased jitter caused by the passage of clocks through lookup tables and general routing

  • output jitter may change after each place & route operation; care must be taken to perform measurements prior to each firmware release

This clock mux includes sequential logic in the clock domains of all input clocks. For its correct functionality, the previously selected clock must be active for at least three cycles after the switch to another clock is requested.

Ports

Name	Description	Type
clks_i	Vector of input clock signals among which to choose the output	std_logic_vector(num_clocks - 1 downto 0)
clk_sel_i	Mux selector bus, expressing the choice of the input as a binary address	std_logic_vector(clog2(num_clocks) - 1 downto 0)
clk_o	Output clock	std_logic

Implementation Details

The module is an extension of the concept shown in the following figure to more than two input signals. The figure and implementation concept can be found in the design recommendations of Intel Quartus Prime Pro Edition User Guide, at this website

To switch between the clocks, a sequence of operations are carried out by the module:

1. A combinational converter produces a one-hot encoded version of the mux selector signal

2. Each input clock controls a train of three flip-flops, the last one (ena_r2) being negative-edge-triggered

3. Each flip-flop train receives its bit of the one-hot selector as input, but only as long as ena_r2 is low for all the other clocks

   • This means that the enable procedure for a clock does not start before all other clocks are disabled

4. Clocks whose ena_r2 is high are allowed to reach an OR gate which reduces them to a single output

   • Because of the condition at point 3, it is guaranteed that only one clock at a time will reach this gate

   • Because the ena_r2 FFs are negative-edge-triggered, clocks are switched on and off at the output while they are going low, preventing glitches