Signal CDC

Introduction

The signal_cdc module is designed to facilitate cross-clock domain communication while mitigating the risk of metastable conditions. It employs a double buffering technique to ensure reliable data transfer between different clock domains. Additionally, the module includes logic to detect both rising and falling edges in the input signal.

Ports

Signal Name	Description	Data Type
clk_i	Input clock signal	std_logic
input_i	Input data signal	std_logic
output_o	Output data signal	std_logic
rising_edge_o	Output signal for rising edge detection	std_logic
falling_edge_o	Output signal for falling edge detection	std_logic